Flip-flops may refer to sequential circuits that store either a “high” value (power high or logic one) or a “low” value (power low or logic zero). A flip-flop may store a next value that depends on the values of one or more input signals. Conventionally, a flip-flop may include data, clock, set, and/or reset input signals.
A Data (conventionally designated D) input signal is typically clocked into the flip-flop on receipt of a given clock edge and appears at the flip-flop output on the opposite clock edge. Set (conventionally designated S) and Reset (conventionally designated R) input signals are generally unclocked, meaning that when the set or reset signal becomes active (e.g., goes high), the stored value changes immediately, without waiting for the arrival of a clock edge. An active set signal forces the stored value (conventionally designated Q) high, despite the previously stored value. An active reset signal forces the stored value Q low, despite the previously stored value. In set/reset flip-flops (i.e., flip-flops having both set and reset input signals) the set and reset signals are typically restricted such that at most one of them can be active at any given time. Since flip-flop is a fundamental building block of modern digital designs, there is always a need to minimize its power consumption and area. A new flop-flop design is proposed that would reduce its power consumption and area compared to conventional designs.